BIST scheduling with multi-phase test cloc
Yushan Li · Systems engineering and electronics · 2004
The BIST is the chief DFT technique for SoC testing. To reduce the BIST test time in SoC, an efficient way is to increase parallel tests. But too many parallel tests will lead to over power and do harm to the SoC. To solve this problem, under the power limitation, a multi-phase-clock based test scheduling method is proposed. This method uses the genetic algorithm to arrange the BIST modules into each clock and determine the test sequence. Experiment results of an ISCAS circuit based SoC show that this method could schedule test efficiently.