A Pipeline Architecture for High Speed FIR Filters
Han Zhou-an · Telecommunication Engineering · 2002
The technique about how to use pipeline architecture to design high speed FIR filters is illustrated through the process of designing a 13-tap FIR digital filter called digital square root raised cosine filter, for filtering the signals without intersymbol interferences. Taking into account of the capacity of FPGA, an analysis of the resources consumed by the FIR filter is made, and based upon the analysis a conclusion is drawn.