FPGA implementation of LDPC encoder in DVB-S2
Lin Wang · Journal of Chongqing University of Posts and Telecommunications · 2008
This paper analyses the characteristics of the LDPC code in DVB-S2,and proposes an encoding architecture for FPGA implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60.The design method adopts many BlockRAMs to process all the parity bits relating to the same information bit in parallel,thus improving the encoding speed.Synthesis results show that this encoder has a throughput about 49.95 Mbps,which satisfies the demand of DVB-S2 at the cost of low resource occupation.