Optimized Design on Carry Look-ahead Adder
Yuan Ha · Communications technology · 2014
This paper introduces a novel design method based on the analysis of CLA( Carry Look-ahead) logic algorithm. The wide adder adopts the multilayer CLA block technique between groups,with four bits as a group,to reduce the hardware delay and achieve the parallel and high-speed purpose. The key point is to optimize the design of full adder at the transistor level,and thus to reduce the circuit delay,area and power consumption. Simulation result indicates that compared with the traditional structure,the delay,area and power consumption of the 16 bit CLA could be significantly improved,and the optimized effect in the environment of SMIC65nm thus be achieved.