Enhancing Hardware Security with Emerging Transistor Technologies
Yu Bi, Xiaobo Sharon Hu, Yier Jin, Michael Thaddeus Niemier, Kaveh Shamsi, Xunzhao Yin · 2016
We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random num- ber generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.