Functional Verification Based on Generation of Constraint-Random Testbench
Jun Yang · Journal of Electron Devices · 2005
In SOC system on chip design , traditional functional verification method is confronted with some special challenges :(1)hard to make complex verification scenarios. (2)difficult to cover corner cases. While the method of functional verification based on generation of constraint-random testbench can randomly generate testbenches limited by some constraints, it resolves the challenges effectively. This paper emphersizes how to make verification environment with Specman and E language in SOC design and uses this method to verify memory controller of a SOC as a example. As result of verification, the coverages of complex verification scenarios and corner cases all reach 100%. MPW shows that the modules verified by this method meet the design specification.