Design of 32-bit floating-point multiplier based on improved carry-select adder
Zhao Hong-shen · Modern Electronics Technique · 2013
On the basis of the modified Booth encoding,Wallace tree structure and carry-select adder,a new structure of 32-bit float point multiplier is proposed,which can shorten its critical path delay by cutting the carry chain.The carry selection of each level of the carry-select adder comes from the upper carry output.The new structure can produce the 16th bit of the mantissa.By comparing it with the relative output bit of the Wallace tree,the carry which comes from the former bit can be got to achieve the carry selection.By using the new structure,a 4-stage pipeline float point multiplier supporting IEEE754 standard is implemented on Altera' s FPGA device EP2C70F896C6.The time-sequence simulation shows that the critical path delay of the multiplier is 5.9 ns,less than that of the traditional multiplier,which is 6.4 ns.