Design of a VLSI architecture for a high performance QAM initial demodulator for HDTV receiver
Jiang Ai-peng · Journal of Circuits and Systems · 2007
An all-digital QAM initial demodulator architecture is presented for HDTV receiver chip. This initial demodulator incorporates a digital mixer, DDFS and low-pass filter. This paper presents a direct digital frequency synthesizer (DDFS) based on Least Square (LS) approximation to optimize sine-cosine wave to make SFDR in worst situation less than -75dBc. At the same time, by applying methods of complex quadrature signal and expand filter’s coefficients, it optimizes the architecture of low-pass filter and reduces the area of circuit.