Exploiting Fine-Grained Parallelism with the Fast Inter-Core Communication Mechanism on Multi-Core DSPs
Shuming Chen · Computer Engineering and Science · 2009
Some digital signal processing algorithms have dependence between relatively very small amounts of computations,so partitioning these algorithms across multiple cores needs to exploit fine-grained parallelism.However,the capability of exploiting fine-grained parallelism is constrained by the fast inter-core communication mechanism.In this paper,we propose a new inter-core communication mechanism for multi-core DSP:TSRF(Tagged Share Register File).TSRF is shared by all DSP cores,and each register in TSRF is correlated with a tag bit which provides the low cost synchronization support for inter-core communication.We construct a cycle-accurate architecture simulator for a multi-core DSP which integrates TSRF.The number of DSP cores is four.Through detailed simulation,we evaluate the efficiency of TSRF with typical digital signal processing algorithms:IIR filter and ADPCM encoder/decoder.Compared to the result on the single-core DSP,the multi-core DSP which integrates TSRF attains the speedup of about 1.8,1.2 and 1.9 respectively.