Implementation of Encoder for LDPC Codes with FPGA
Yongshan Liu · Journal of Military Communications Technology · 2006
The UR algorithm reduces the complexity of LDPC codes encoder markedly.The design and implementation of encoder for LDPC codes were introduced.An implementation for a rate 0.5 regular length 343 LDPC code encoder with XILINX FPGA was presented.The encoder is of low complexity and high flexibility and suits all kinds of LDPC codes.