Static Timing Analysis for the Line-to-Line Crosstalk Phenomenon
Huawei Li · Computer Engineering and Science · 2005
Current design trends show that crosstalk issues in deep sub-micron can cause severe problems of design validation and test. Although the number of all possible crosstalks that may cause faults is huge, the number of those that really cause faults is much smaller. So, the efficiency of test generation can be improved if the static timing analysis (STA) is done before it. In this paper, we introduce the analysis of crosstalk into the STA process. The overlapped transition pairs fault model is used based on the line delay model. Only transitions overlapped with the longest paths are considered during faults selection. Experimental results for the ISCAS'89 benchmark circuits show that the number of faults is reduced significantly to less than 10% of the original number of candidates. The CPU efficiency of our experimental results is better than that of the previous work.