Implementation of high-performance FPGA based Viterbi decoder in receiver for satellite navigation
Hu Qiang · Modern Electronics Technique · 2012
The existing convolutinal code decoder-Viterbi decoder in satellite position receiverbe is confronted with the problems of multi-resource occupation and long time processing.A method of using parallel plus selection butterfly unit is adopted to reduce the ocupation of processer resource and increase the processing speecd.A high-performance Viterbi decoder was designed with hardware description language on the FPGA platform.It works on GPS and GALILEO receiver as a general decoder of GPS L2 and Galileo E1 frequency point receiver,and can reduce the resource occupation and improve the processing speed of receivers.