Oracle-Guided Incremental SAT Solving to Reverse Engineer Camouflaged Logic Circuits
Duo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb · 2016
Layout-level gate camouflaging has attracted interest as a countermeasure against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gates in a circuit are camouflaged, and each camouflaged gate layout can implement a few different logic functions. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing which logic functions the camouflaged gates implement.