Structured hardware compilation of parallel programs
Wayne W. Luk, David E. Ferguson, Ian Page · 1994
A major bottleneck in automatic hardware synthesis is the time to place and route the netlist produced by a hardware compiler. This paper presents a method which exploits the syntax of the source program to guide its layout in a deviceindependent manner. The technique has been used in prototyping a hardware compiler for a commercially-available device, the Algotronix CAL1024 FieldProgrammable Gate Array. The potential of this approach is evaluated. INTRODUCTION Recent work has shown how parallel programs, in a language such as occam (Inmos 1984), can be compiled into synchronous and asynchronous circuits (Page and Luk 1991, Weber et al 1992). This approach enables the rapid generation of custom hardware from a high-level description; it also provides a uniform framework for developing and verifying systems with both hardware and software components. At present many hardware compilers produce from a source program a netlist description which specifies the appropriate connection of circ...