A dynamically reconfigurable microprocessor architecture
Mitchell Scott, K.C. Smith · 1980
This thesis examines the use of bit slice microprocessors in providing a multicomputer system with dynamic reconfiguration capabilities. These capabilities allow reconfiguration, under software control, of the system hardware into a variable number of processors of different characteristics (such as word size and instruction set). There are many potential uses of such capabilities in the areas of multiprogramming, parallel processing, and fault tolerant systems. The reconfiguration capability introduces a number of issues concerning processor function modularization, that do not arise in fixed architectures. The thesis examines these issues and shows potential processor modules that are realizable with current LSI technology. A dynamically reconfigurable architecture has problems in providing efficient connections between the processors and shared input, output, and file storage devices. This thesis examines an asynchronous bus structure and associated bus window devices that solve these problems. The structure examined equips each processor with a local bus for memory and dedicated devices, with access to one or more global shared resource buses. The structure supports processor and direct memory access device controlled data transfers, both intra- and inter-bus, as well as intra-bus interrupts and interrupt transfers between buses. This thesis provides details of the bus lines, the bus protocols, and the operation of the various bus windows. It examines the problem of potential deadlock, and its resolution, and the problem of equitable bus sharing in periods of high bus contention.