Recursive Hierarchical DFT Methodology with Multi-level Clock Control and Scan Pattern Retargeting
Dan Trock, Rick Fisette · 2016
The value of hierarchical DFT methodologies is well established today. Generating scan patterns at the core level to determine coverage and debug pattern issues is a common practice in today's large SoCs. However, the pattern mapping process from core to chip level has remained an error-prone task that requires significant verification effort. This leads many SoC designers to regenerate patterns at the SoC level and not fully realize the benefits of a hierarchical approach. Since the introduction of automated pattern mapping by EDA tool vendors, leveraging the hierarchical approach has become easier. In this paper we present a multi-level clock control architecture that enables deployment of recursive hierarchical DFT with scan pattern retargeting at multiple levels. The resulting silicon-proven implementation demonstrates ATPG runtime speed-up and memory savings of 10X. Test coverage is maintained and test pattern count is reduced while DFT tapeout schedule is significantly improved.