An Efficient Embedded DRAM Testing Algorithm With Multiple Memory Arrays
S. Jayaprabha, B. Ramesh, S. Premalatha · 2013
With the strong need to an effective and economic embeddedmemory core in the Soc, researchers attempt to carry commodity DRAM’s advantages from a commodity memory into a Soc. In the past decade, a lot research effort has been put into the area of the embedded-DRAM (eDRAM) technologies to reduce eDRAM’s process adders to the CMOS process. However, few previous research works have discussed the testing strategies used for eDRAMs, which cannot be directly carried from the testing of commodity DRAMs. In this project, first compare the eDRAM testing to the commodity-DRAM testing and SRAM testing since an eDRAM core utilizes the DRAM cells with the SRAM interface. Then, list the fault models which should be specially considered in the eDRAM testing and find out the corresponding test sequence for each fault model. The main objectives of this project include (1) develop a minimal test algorithm for eDRAM testing, (2) develop an effective scheme to shorten the retention-test time in eDRAM testing based on increasing the temperature, which is a special function used in eDRAMs compared to commodity DRAMs.