An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication
Shiann-Rong Kuang, Chih-Yuan Liang, Chun-Chi Chen · IEEE Transactions on Circuits & Systems II Express Briefs · 2016
To achieve low latency, existing radix-4 scalable architectures for word-based Montgomery modular multiplication usually suffer from high design and hardware complexities. This brief presents a simple compression scheme and circuit to remove the data dependence in the accumulation process and accomplish one-cycle latency without quotient pipeline. The complex computation and encoding of quotient digits are thus avoided, leading to up to 10.6% and 17.7% reductions in area and power than previous work while maintaining very high performance. Consequently, the proposed radix-4 scalable architecture appears to be very suited for low-complexity and low-power cryptographic applications.