New techniques for synthesis and testing of asynchronous circuits
Savita Banerjee · 1996
Asynchronous circuits have enormous potential for achieving high performance and low power consumption. However, the inherent complexities associated with the design and testing of asynchronous circuits have prevented their widespread use in industrial applications. This dissertation investigates asynchronous circuit synthesis and testing. Existing asynchronous circuit synthesis techniques ignore initializability considerations and may produce uninitializable implementations. We present a new synthesis method that ensures initializability. We show that for functionally initializable designs, careful don't care assignment is sufficient to guarantee initializability. However, initializable implementations cannot be obtained from a functionally uninitializable specification. We develop a technique that transforms such specifications into equivalent, functionally initializable specifications. We exploit the presence of concurrency in the specification to provide the necessary flexibility to make these transformations. ATPG results on several benchmark circuits show that uninitializable circuits have zero fault coverage making them untestable. Our synthesis for initializability technique was able to achieve initializability at low cost in terms of literals and by sacrificing minimal concurrency. The fault coverages for initializable designs were significantly higher than for the uninitializable circuits produced by earlier methods. Tests generated for asynchronous circuits using existing methods can be invalidated if the delay-dependent nature and unstable states of the circuit are not considered. Test invalidation is a major concern, since it may reflect in a decrease in fault coverage. We develop a sophisticated synchronous test model (STM) that captures the essential behavior of the asynchronous circuit under test. The STM enables us to use any synchronous test generator to derive tests for asynchronous circuits with greater accuracy. We prove that test invalidation due to unstable states is completely eliminated in our new test methodology. We safeguard against hazards by validating the tests using an asynchronous fault simulator. Experimental results on several benchmark designs show that the proposed testing methodology consistently generates tests with high fault coverage and absolutely no test invalidation. The STM can also be used to generate tests for faults in embedded asynchronous systems, gated-clock circuits, and feedback bridging faults in both combinational and sequential circuits. Experimental results demonstrate the suitability of the STM for these applications.