FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories
Syed Azhar Ali Zaidi, Abuduwaili Tuoheti, Maurizio Martina, Guido Masera · IEEE Design and Test · 2015
In this article, the authors implement an FPGA simulator that accelerates the performance evaluation of very long QC-LDPC codes, and present a novel 8-KB LDPC code for NAND flash memory with better performance.