Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths
Xiaobo Yin, Feng Nan Yu, Zhenguo Ma · IEEE Transactions on Circuits & Systems II Express Briefs · 2016
This brief presents a new algorithm optimized for radix-2 real-valued fast Fourier transform (RFFT) through rigorous formula derivation. Based on that, a novel two-parallel pipelined radix-2 RFFT architecture is proposed with only real datapaths instead of hybrid datapaths. The architecture takes advantage of saving the arithmetic resource in the time-division multiplexing approach to achieve 100% hardware resource utilization. Thereby, it reduces the required number of complex multipliers from log2N-2 to (1/2)(log2N -3), in contrast with existing two-parallel pipelined architectures. The experimental result shows that the proposed two-parallel architecture can reduce the slice and power consumption by a factor of 30% compared with a recently published work for a 64-point CFFT. Furthermore, a systematic method is also explicated to generalize the architecture to higher level of parallelism and higher radix.