VLSI architectures for fast matrix inversion
Kai Hwang, J.C. Hausman · OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) · 1983
Summary form only given. Two new systolic array structures are proposed for fast matrix inversion by VLSI hardware approaches. These multiprocessor architectures are extremely useful in real-time applications such as signal/image processing, robotic system control, and machine discriminant analysis. The first array is a pipeline of o(n) processors for finding the inverse of a nonsingular n*n matrix in o(n/sup 2/) time. The second array of o(n) processors is proposed to invert an n*n matrix b=a+c, given the inverse a/sup -1/ of a and rank (c)=k. The proposed systolic array structures and their application algorithms have been correctly verified by computer simulations. Timing, speed, and hardware complexities of the proposed VLSI matrix inverters are discussed. 6 references.