Low power JPEG2000 5/3 discrete wavelet transform algorithm and architecture
Kay-Chuan Benny Tan · ERA · 2004
With the advances in VLSI digital technology, many high throughput and performance imaging and video applications have emerged and increased in usage.At the core of these imaging and video applications is the image and video compression technology.Image and video compression processes are by nature very computational and power consuming.Such high power consumption will shorten the operating time of a portable imaging and video device and can also cause overheating.As such, ways of making image and video compression processes inherently low power is needed.The lifting based Discrete Wavelet Transform (DWT) is increasingly used for compression digital image data and is the basis for the JPEG2000 standard (ISO/IEC 15444).Even though the lifting based DWT has resulted in several implementations of this algorithm, there is no work on the low power realisation of such an algorithm.Recent JPEG2000 DWT implementations are pipelined data-path centric designs and do not consider the issue of power.This thesis therefore sets out to realise a low power JPEG2000 5/3 lifting based DWT hardware architecture and investigates whether optimising at both algorithmic and architectural level will yield a lower power hardware.Besides these, this research also ascertains whether the accumulating Arithmetic Logic Unit (ALU) centric processor architecture is more low power than the feed-through pipelined data-path centric processor architecture.A number of novel implementation schemes of the realisation of a low power JPEG2000 5/3 lifting based DWT hardware are proposed and presented in this thesis.These schemes aim to reduce the switched capacitance by reducing the number of computational steps and data-path/arithmetic hardware through the manipulation of the lifting-based 5/3 DWT algorithm, operation scheduling and alteration to the traditional processor architecture.These resulted in a novel SA-ALU centric JPEG2000 5/3 lifting based DWT hardware architecture that saves about 25% of hardware with respect to the two presented existing 5/3 DWT lifting-based architectures.The proposed SA-ALU centric architecture also allows innovative scheduling and a novel embedded extension algorithm to be incorporated into its main operation.The embedded extension algorithm saves more than 50% of memory and power by doing away with explicit data extension operations entirely.Optimisation at architectural level also results in a novel addressing architecture called the dyadic multi-segments multi-level one-hot addressing architecture (MSML-OHA).The MSML-OHA reduces power by 20% through reducing switched capacitance by isolating and confining switching activities into a small local area by segmentation.A further reduction of 59% is achieved in the dyadically structured MSML-OHA (DMSMIL-OHA) when this is combined with the shared address lines architecture bought about by innovative scheduling.