Combined Resource Allocation and Test Generation for On-Line Test Structures
Uroš Kač, Franc Novak, Chouki Aktouf, Chantal Robach · 1999
This paper presents a cost-effective approach that allows complex circuits and systems to be on-line tested. The approach combines a test logic insertion technique and a method that allows tests to be generated from a high level specification. The test logic insertion technique takes advantage of functional unit idle cycles that are otherwise lost during the execution of useful computations. A concurrent test structure, which cycles test vectors through idle functional units, is synthesised within the circuit along with the original algorithm, avoiding test-time overheads. Tests are generated at the highest level in the synthesis process in order to allow test quality to be estimated. The efficiency of the overall approach is illustrated on a simple application.