FPGA based hardware scheduler for multiprocessor systems
Habibullah Jamal, Zeeshan Khan, Muhammad Mohsin Rahmatullah · 2008
This paper presents a hardware implementation of a scheduler for multiprocessor systems that minimizes the processor time for scheduling activity. Code fetch time overhead is also reduced by attempting to cluster similar tasks on one processor. Processors not in use are switched to power saving mode and they are only turned on if there is no other processor to take on the required activity.