Bias Optimization for Noise Reduction in Focal Plane Arrays
Kirk Reiff · Journal of International Crisis and Risk Communication Research · 1987
A gain enhanced common gate transresistance circuit is typically used as the coupling circuit between detector and multiplexer in a focal plane array. At an operating temperature of 77 degrees Kelvin, the dominant noises in the system are shot noise and 1/f noise. The 1/f noise corner frequency of the CMOS amplifiers used in focal plane arrays can .be as high as 10 kHz. In this paper it is shown that the 1/f noise corner frequency contributed to the system noise by the amplifier is a function of the bias voltage applied to the photodiode detector. Specifically, as the reverse bias to the detector increases, the 1/f noise corner contributed to the system by the amplifier decreases, while the 1/f noise corner contributed to the system by the photodiode increases. This implies there is a trade off between the amplifier contributed 1/f noise corner and the photodiode contributed 1/f noise corner. Therefore there is an optimum bias voltage, which is not zero volts, where the overall noise in the system will be at a minimum.