A Design of Transputer Core and its implementation in an FPGA
Makoto Tanaka, Naoya Fukuchi, Yutaka Ooki, Chikara Fukunaga · 2004
We have made an IP (Intellectual Property) core for the T425 transputer. The same machine instructions as the transputer are executable in this IP core (which we call the TPCORE). To create an IP core for the transputer has two aspects. On one hand, if we could succeed in building our own one and putting it in an FPGA (or VLSI chip), we could apply it as a core processor in a distributed system. On the other hand, if we can extend our transputer development from a very conventional one to more sophisticated ones, as Inmos proceeded to the T9000, we hope to find technological breakthroughs for the bottlenecks that the original transputer had - such as the restriction of the number of communication channels. It is important to have an IP core for the transputer. Although the TPCORE uses the same register set with the same functionality as the transputer and follows the same mechanisms for the link communication between two processes and interrupt handling, the implementation must be very different from original transputer. We have extensively used micro-code ROM to describe any states that the TPCORE must take. Using this micro-code ROM for the state transition description, we could implement the TPCORE economically on FPGA space and achieve efficient performance.