A globally asynchronous locally synchronous configurable array architecture for algorithm embeddings
Bo Gao · ERA · 1996
Advanced VLSI/ULSI technologies have made it possible to realise parallelism and pipelimng processing principles at affordable cost.One of the consequences is that more and more algorithms are now directly implemented in hardware.The configurable hardware algorithm approach has the potential to combine the performance of hardware algorithms and the flexibility of software algorithms at the user level.On the other hand, system timing design problems become one of the determining factors on design complexity, correct system function and high performance.This timing problem plays an even more important role in configurable systems.patiently supervised me and given me a lot of encouragement all the way through my research work.He also carefully proof read the draft of this thesis and has made many useful comments.Special thanks also go to Professor David Kinniment from University of Newcastle upon Tyne who has helped me to clarify the synchronisation issue discussed in this thesis.I would like to thank the department of Computer Science of Edinburgh University where an excellent research environment and computing facilities are provided, and from where I have obtained substantial knowledge on computer architectures and skills on programming.I would also like to acknowledge the support of Sino-British Friendship Scholarship Scheme which made my research in Britain a reality.