Design of a VLSI Packet Buffer
Neil Edward Barrett · Open Scholarship Institutional Repository (Washington University in St. Louis) · 1988
This paper describes the design of the Packet Buffer Chip. Packet Buffers are FIFO queues used for buffering packets and synchronizing a Switch Fabric (SF) and its associated Fiber Optic Links (FOLS) in the Broadcast Packet Switching Network. This chip will be fabricated in 2.0 UM CMOS technology.