Self-timed field programmmable gate array architectures
Robert Payne · ERA · 1997
Dynamic hardware systems exploit the in-system reconfigurability of Field Programmable Gate Arrays (FPGAs), but are currently limited by the delay properties of synchronous FPGA architectures.Synchronous circuits are difficult to manipulate dynamically, since this alters their internal delays.The speed-independent properties of self-timed circuits overcome this problem, thus allowing the full benefits of dynamic reconfiguration to be exploited.The general properties of self-timed systems, such as modularity, low power and data dependent delays also provide benefits to less dynamic FPGA systems as well.This thesis introduces a model for self-timed FPGA architectures called STACC (Self-Timed Array of Configurable Cells).STACC architectures replace the global clock of an FPGA with an array of timing cells that provide local self-timed control to a region of logic blocks.STACC differs from previous self-timed FPGA architectures in that it does not disrupt the structure of the logic blocks.The STACC model is used to produced a self-timed version of the Xilinx XC6200 FPGA.Example circuits for the self-timed XC6200 demonstrate the benefits of self-timing for implementing dynamic hardware systems.Evaluation of the architecture shows that the implementation overhead of the timing array is reasonable, and that the self-timed XC6200 has the potential to out-perform the synchronous XC6200 through use of data dependent delays.Current synchronous-oriented FPGA architectures pose problems for the implementation of self-timed circuits.The assumptions made in self-timed communication protocols are often not maintained by synchronous FPGA architectures.The approach taken in this thesis is to develop self-timed FPGA architectures to overcome the problems with current FPGAs.The thesis introduces a new model for self-timed FPGA architectures called STACC (Self-Timed Array of Configurable Cells).In STACC, the global clock of a synchronous FPGA architecture is replaced with an array of timing cells.These timing cells provide local timing control to regions of logic blocks, which are left unaltered from the original synchronous FPGA architecture.The clear split between timing cells and data cells (logic blocks) in STACC reflects the split in self-timed bundled-data protocols between control path and data path.To demonstrate the viability of STACC, the STACC model is applied to the Xilinx XC6200 FPGA architecture.The Xilinx XC6200 was chosen since it is a recent architecture (first silicon in 1995), and that it includes features for the use of dynamic hardware.The self-timed XC6200 architecture is used to construct circuits parameterised at run-time, which demonstrate the benefits of self-timing for dynamic hardware systems. Thesis StructureThe thesis consists of four main parts.The introductory chapters present background material on FPGAs and self-timed systems, and outline the potential benefits of self-timed FPGA systems.The second part of the thesis introduces the STACC model for self-timed FPGA architectures, and develops the circuit elements required for the construction of STACC architectures.The third part of the thesis concerns the application of the STACC model to the Xilinx XC6200 FPGA architecture.Finally, the thesis concludes with a summary of the main results and a discussion of possible future work.Figure 1.1 summaries the structure of the thesis and shows the relationship between the chapters.Below, a chapter by chapter summary for each part of the thesis is given.'A 1.2.4 Conclusions Chapter 12 summarises the main results of the work.The chapter ends with a discussion of possible directions for future research. ContributionsThis thesis makes original contributions in a number of areas.The main contributions are listed below.These points are expanded upon in Chapter 12, which summarises the conclusions of the thesis. Self-timed Dynamic Hardware:A key contribution of the thesis is the identification of the benefits of self-timed circuits for implementing dynamic hardware systems.Previous work on self-timed circuits for FPGAs have concentrated only on the prototyping of self-timed systems.STACC: is a new model for creating self-timed reconfigurable architectures.Unlike previous self-timed FPGA architectures (MONTAGE, PGA-STC), STACC-based architectures do not alter the structure of the logic blocks for self-timing. Self-timed Reconfigurable Elements:The thesis introduces a number of new self-timed elements, potentially of wider use in self-timed design: the Q-Merge/Select Pair, the reconfigurable C-Muller gate, the STACC timing cell and handshaking crossbars.Self-timed XC6200: Using the STACC model, this thesis presents the design, simulation and evaluation of a new self-timed FPGA architecture based on the Xilinx XC6200.Run-Time Parameterised Circuits: The circuits developed for run-time parameterisation on the self-timed XC6200 are of note, due to the hierarchy of parameterisation, and the benefits arising from self-timing.Some of the design techniques developed, such as the abstract block size, are applicable to XC6200 designs in general. Current Sensing Completion Detection (CSCD):The thesis provides insight into the potential benefits of the CSCD delay scheme and proposes the use of CSCD for meta-stability resolution. E1IN CAL [3], provide another option for input/output.Data can be read and written into the array using the SRAM interface.Potentially, using this interface could alleviate the need for other input/output pins altogether, but currently no FPGAs have adopted this approach.A conflicting objective to minimising the number of pins is to allow the array to be naturally extended, which requires all input and outputs to be provided as pins.This is extremely costly; of all the FPGAs discussed, only CAL [3] manages this, and this is through its use of ternary signalling.Even providing all the necessary extensions, an array of FPGAs cannot be treated as a uniform array due to the magnitude of off-chip delays.One method of providing a large array of FPGA chips, which is as close as possible to one uniform array of function blocks is WSI (Wafer Scale Integration).An example of this approach is the Teramac [108] system built by HP Laboratories, which integrates several FPGAs on one MCM (Multi-Chip Module).Also Isshiki et al [64] have built a MCM with 12 Xilinx XC3042 chips and an Aptix FPID (Field Programmable Interconnect Device) as additional interconnect. Configuration MemoryCurrent FPGAs use two basic types of configuration memories: fuse based and SRAM based.The key difference between these two types of configuration memory is that SRAM based designs have the the potential to be reconfigured in-system, whilst fuse based designs need to be programmed externally to the system in a special programmer.However, fuses can be implemented more compactly, which leads to a different style of architecture from SRAM based ones, where the configuration memory is relatively expensive to implement.These two types of configuration memory are discussed below.'-'SI.'