PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015
In 3-D-stacked memory chips, the problem of power supply integrity (PSI) is aggravating due to the additional through-silicon-via resistance and the higher current density in 3-D power delivery network. In particular, for the 3-D phase-change memory (PCM) well known for its high-amplitude programming current, IR-drop violation poses a serious threat that enforces a strict guard band of requesting concurrence, and consequently reduces the write throughput. This paper presents the implication of an IR-drop phenomenon in a 3-D PCM cube, and investigates IR-drop's impacts on write management in the PCM. From the obtained SPICE simulation results, we find that the issued writes have to meet the IR-drop constraint to be reliably processed, and then propose a PSI conscious write scheduler to improve the write performance within the constraint of the IR-drops and the power budget in the 3-D PCM cube. First, a Bloom-filter-based method is proposed to avoid the invalid write decisions for the PCM. Second, to support fine-grained write management in the cutting-edge PCM, we develop an inexpensive approach, weighted token assignment (WTA), to filter out PSI-unsafe write decisions by employing a support vector machine-based learning model. Last, a write reordering policy is proposed to cooperate with WTA and optimize the total write throughput for better memory performance. In the simulated hybrid main memory composed of both dynamic random access memory and 3-D PCM, the proposed scheduler significantly improves the write throughput.