Fast and Area Efficient RSA Cryptosystem Design Using Modified Montgomery Multiplication for FPGA Applications
Desiree Juby Vincent · 2013
RSA(Rivest-Shamir-Adleman) cryptosystem is one of the most widely used public key cryptosystem.The importance of high security and faster implementations paved the way for RSA crypto-accelerators, hardware implementations of the RSA algorithm.The whole RSA includes three parts: key generation, encryption and decryption process. The RSA operation is a modular exponentiation, and its security lies in its inability to efficiently factorize large integers. Basically, the modular exponentiation with a large modulus is usually accomplished by performing repeated modular multiplications, which is considerably time-consuming. As a result, the throughput rate of RSA cryptosystem will entirely dependent on the speed of modular multiplication and the number of performed modular multiplications. To speed up the process of modular multiplication, Montgomery's algorithm is recognized as a very efficient solution, in which it replaces the trial division with a series of additions and division by a power of two. Therefore, it is well suited to hardware implementation and consumes less power and uses smaller amount of space in the FPGA compared to other multiply and reduce methods. This work describes the design of an efficient RSA cryptosystem that uses a modified Montgomery algorithm to increase the speed of modular multiplication and a very fast parallel prefix adder ( Kogge- Stone Adder) is employed to reduce the critical path .The design architecture is coded in VHDL, synthesized using Xilinx ISE 12.1 and simulated using Modelsim. Experimental results shows that the modified design obtain the best delay performance compared with the standard design.