Exploring the Memory Hierarchy for Packet Processing Applications
K Bahareh Safaei · International Journal on Computational Science & Applications · 2012
In the future, network processors must process more computation-intensive network applications and internet traffic and packet-processing tasks become heavier and sophisticated. Since the processor performance is severely related to the average memory access delay and also the number of processor registers affects the performance, cache and registerfile are two major parts in designing embedded processor architecture. Although increasing cache and registerfile size leads to performance improvement in packet processing tasks in high traffic networks with too much packets, the increased area, power consumption and memory hierarchy delay are the overheads of thesetechniques. Therefore, implementing these components in the optimum size is of significant interest in the design of embedded processors. This paper explores the effect of cache and registerfile size on the processor performance to calculate the optimum size of these components for network applications. Experiment a results show that although having bigger cache and registerfile is one of the performance improvement approaches in network processors, however, by increasing the size of these parameters over a threshold level, performance improvement is saturated and then, decreased.