Empirical performance study of speculative parallel processing on commercial multi-core CPU with hardware transactional memory
Kanemitsu Ootsu, Yutaka Matsuno, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba · 2015
To achieve performance improvement by using multi-core processor, efficient utilization of thread-level parallelism is essential. However, conventional parallel processing cannot efficiently utilize potential parallelism within program code, since there are various dependencies within program code to be kept strictly. For this problem, speculative parallel processing is considered useful. However, to realize the method on conventional commercial multi-core processors, it is necessary to manage speculative data by software, since conventional processors do not have hardware support for speculative data. Practical performance improvement has been difficult to attain, since its runtime overhead is large. In this research, we focus on hardware transactional memory (HTM), that is provided on the commercial multi-core processors released from Intel recently. This research aims to reduce the runtime overhead caused by the management of speculative data in speculative parallel processors by using HTM, to achieve an efficient speculative parallel processing on commercial multi-core processors. In this paper, as our first step, we evaluate the performance of the pre-computation method using helper-thread, that is a speculative parallel processing technique, by using Dijkstra program that solves the shortest path program on graph data. We quantitatively show the effect of HTM on parallel processing.