Towards High-Performance Bufferless NoCs with SCEPTER
Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan · IEEE Computer Architecture Letters · 2015
In the many-core era, the network on-chip (NoC) is playing a larger role in meeting performance, area and power goals, as router buffers contribute greatly to NoC area and power usage. Proposals have advocated bufferless NoCs, however a performance wall has been reached such that high throughput performance has not been extracted. We present SCEPTER, a high-performance bufferless mesh NoC that sets up single-cycle virtual express paths dynamically across the chip, allowing deflected packets to go through non-minimal paths with no latency penalty. For a 64 node network, we demonstrate an average 62 percent reduction in latency and an average 1.3× higher throughput over a baseline bufferless NoC for synthetic traffic patterns; with comparable performance to a single-cycle multihop buffered mesh network with six flit buffers, per input port, in each router.