Programmable High Speed 8-Bit Binary Incrementer Decrementer
sssist Sehore (m.p), Jaikaran Singh, Mukesh Tiwari, Zuber Khan · International Journal of Engineering Trends and Technology · 2015
#electronics & communication department,sssist Sehore(m.p), india This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area. We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle.