Design of Non-pipelined LC3 RISC Microcontroller
Devyani Gera, Mehul Garg · IOSR Journal of Computer Engineering · 2014
This paper highlights the designingof data and control path of a non-pipelined LC3 microcontroller with a 16 bit Reduced instruction set.The designing was done using a Hardware Descriptive Language (HDL) System Verilog on the platform Questasim Simulator.We have demonstrated the use of this RISC microcontroller using basic ALU operations-ADD, AND & NOT, and a memory operation-Load Effective Address (LEA).The 16 bit reduced instruction used in the designing has been chosensuch that it's computing ends in exactly 5 clock cycles.