CHIPSCOPE Implementation of CRC circuit architecture
G. Shanthi · IOSR Journal of VLSI and Signal processing · 2013
Cyclic Redundancy Check is an established technique for detecting errors on serial data communication links and in mass storage devices. A frame check sequence is appended to the message for transmission error detection in Many (high-speed) serial data communication protocols.The common hardware solution for CRC calculation is the linear feedback shift register (LFSR), consisting a few Flip Flops and Logic Gates.CRC is the preferred and most efficient method used for detecting bit errors produced from medium related noise.Data storage is another area where CRC error detection is becoming increasingly important.CRC checks to be executed at high speed as well as parallel processing.The ability of CRC implemented in hardware to be reconfigurable to handle new Generator polynomials will offer a key advantage in this fast developing area.The reconfigurable CRC circuit that has been implemented can quickly switch between any polynomial gives it a key advantage over the other circuits.In this paper it is proposed CHIPSCOPE Implementation of a fully field programmable, architecture for a CRC computation circuit.The resulting architecture is able to support all types and sizes of CRC polynomial, for all types of protocols and data encryption.The architecture has been authored in VHDL, synthesized, and implemented using Xilinx ISE Foundation 10.1i, chipscope.For Behavioral simulation, Place and Route simulation Modesim6.0 is used.