A Decimal Floating Point Arithmetic Unit for Embedded System Applications using VLSI Techniques
Rajeshwari Mathapati, Shrikanth Shirakol · International Journal of Engineering Trends and Technology · 2014
With the growing popularity of decimal computer arithmetic in scientific and commercial financial and internet based applications, hardware realization of decimal arithmetic algorithm is gaining more importance. Hardware decimal arithmetic unit serve as an integral part of some recently commercialized general purpose processors, where complex decimal arithmetic operations such as multiplication, have been realized by rather slow iterative hardware algorithms. The widely used IEEE standards, IEEE 754-1985 based binary floating point format and IEEE 754-2008 standard based decimal floating point (DFP) format uses high precision formats, which are generally useful for astronomical or scientific calculations. For simple applications, such a precision is not required and is an addition overhead. Therefore the another format named Immanuel Decimal Floating Point (IDFP) Format is presented and can be used for embedded system applications, which uses commonly used precision. IDFP can be represented either in binary or binary coded decimal (BCD). An arithmetic unit based on IDFP, BCD based number system is developed and is functionally simulated. The adder/subtractor based on BCD adder/subtractor and multiplier developed is a look up table (LUT) based BCD multiplier. The language used for programming is VHDL and is synthesized using Xilinx ISE 13.4 design suite. The results are obtained using Modelsim simulator