A two-stage hog feature extraction processor embedded with SVM for pedestrian detection
Yuan Xu, Li Cai-nian, Xu Xiao-liang, Mei Yue Jiang, Zhang Jian-guo · 2015
A two-stage pipeline architecture for pedestrian detection processor, which embeds the support vector machine (SVM) classifier into the Histogram of Oriented Gradients (HOG) normalization module is proposed. This architecture can effectively reduce hardware resource consumption and can perform pedestrian detection task real-timely. Also, an algorithm is proposed to avoid duplicated detection automatically. The architecture is verified on Spartan-6 FPGA for SVGA resolution video (800×600) at 47 fps/100MHz.