An Efficient Viterbi Decoder Architecture
Kalpana. R Kalpana. R · IOSR Journal of VLSI and Signal processing · 2013
A breadth first trellis decoding algorithm is introduced for application to sequence estimation in digital transmission.The decoding effort adapts to the prevailing noise conditions to yield low average effort.The proposed method of a performance of error correcting in noisy channels to reduce the power dissipation, the decoding speed in much to design a VD for TCM is presented in this paper.VD is used to decode the digital data communications and storage devices without any performance loss.A viterbi decoder uses the viterbi algorithm for decoding a bit stream that has been encoded using Forward error correction based on a code There are other algorithms for decoding a convolutionally encoded stream as well as punctured codes The advandage of VD is errors and correction and digital communication.The pre computation VD could reduce the power consumption by 70% with only 11% reduction of the maximum decoding speed.