FPGA Implementation of Background Subtraction Algorithm for Image Processing
Ms. P.D. Mahamuni, Prof. R. P. Patil · IOSR Journal of Electrical and Electronics Engineering · 2014
The Background Subtraction Algorithm is used to detect the object in the image.The subtraction of the image is pixel based subtraction.Before the subtraction of two images the pre-processing is done using the median filter.After the subtraction is done the segmentation is performed using threshold value.Once the segmentation is completed the morphological filtering is performed on that image to remove the unwanted blobs.System is designed using MATALAB/Simulink block sets.In MATLAB/Simulink the system generator token is used to convert Simulink model logic into the VHDL code which makes it compatible with FPGA.Using the system generator token VHDL code is generated.That VHDL code is synthesis in the Xilinx 14.1 and then .bitfile is downloaded to the Virtex-5 board through JTAG cable and the output image is display on the VGA monitor which is interfaced with Virtex-5 board using DVI connector.