On Acceleration of Logic Synthesis Algorithms using FPGA-based Reconfigurable Coprocessors Technical Report: TR-970010
Jason Cong, J. E. L. Peck · 1997
In this technical report, we present our studies on implementing two fundamental logic synthesis algorithms, tautology checking and binate covering, using an FPGA-based reconfigurable applicationspecific coprocessor. The uses of each algorithm are first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algorithm with the software implementation of the tautology check algorithm in Espresso II [RuVi87]. Our experimental results show that our accelerator is capable of achieving a maximum speedup factor of 2.94 and averaging 1.36 on 110 modified industry benchmarks included with the Espresso II package.