Intellectual Property (IP) Cores and a Logic Fault Test Simulation Environment
Mansour H. Assaf, Lynete Moore, Satyaki Das, Suman Biswas, A.R. Applegate, Emil M. Petriu · 2010
The subject paper develops a low-level logic fault testsimulation environment for embedded systems targetedspecifically towards application-specific integratedcircuits (ASICs) and intellectual property (IP) cores.