FPGA Implementation of FIR Filter Using Bit Serial Arithmetic Technique
MR. SHRIDHAR DEVAMANE · IJIREEICE · 2014
Implementing hardware design in Field Programmable Gate Arrays (FPGAs) is a formidable task.There is more than one way to implement the dsp design for digital FIR filter.The traditional approach is based on application of general purpose multipliers.However, multipliers implemented in FPGA architectures do not allow constructing economic Digital Filters.For this reason, multipliers are replaced by Lookup Tables and Adder Subs tractor, which use Bit-Serial Arithmetic.