Multi-precision squaring on MSP and ARM processors
Hwajeong Seo, Howon Kim · 2014
Efficient implementations of multi-precision squaring and multiplication are crucially important for enhancing the performance of Public-Key Cryptography (PKC) on resource constrained embedded microprocessors, which are widely used in some future technologies, e.g. Internet of Things, sensor networks and smart phones. In this paper, we revisited the “Sliding Block Doubling” (SBD) method for multi-precision squaring proposed by Seo et al., which reduces the number of addition operations with a technique that computes doubling on accumulated results by deferring doubling process. We applied SBD to 16-bit processors MSP430X as well as 32-bit ARM series processors. In order to boost performance, we suggest carry less accumulation method. This method can avoid chain of carry propagations without overflowing. The optimal implementations are conducted and practical experiment results show that a full 160-bit squaring can be accomplished with 570 cycles for MSP430X processor and 180 for ARM general-purpose processors, respectively. When comparing with best previous results on MSP430X and ARM7 series processors, we achieved performance enhancements by 13.9 % and 45.81 %, respectively.