Throughput/Area Trade-Offs of Loop-Unrolling, Functional and Structural Pipeline for Skein Hash Function
George S. Athanasiou, Ηλίας Τσίνγκας, Harris E. Michail, George Theodoridis, Costas E. Goutis · Computer Science & Engineering An International Journal · 2013
In this paper, a design space exploration is performed aiming at developing high-performance hardware architectures for the new cryptographic hash function Skein-512.Three well-known design optimization techniques namely, the loop unrolling, the structural and functional pipeline, are applied, while several design alternatives have been explored to derive optimized FPGA implementations.The proposed architectures have been implemented and evaluated in three Xilinx technologies .Based on the experimental results, when all the three techniques are applied, the best architecture is the 8-round_unroll one with two functional and three structural pipeline stages.To the best of the authors' knowledge, it is the first time that all these three techniques are studied and exploited together for the Skein algorithm.Also, the proposed architectures outperform the corresponding existing ones in terms of Throughput/Area factor from 27% up to 192%, respectively.