AN IMPROVED AND EFFICIENT MAC UNIT AND ITS IMPLEMENTATION IN FPGA
Ranjan Kumar Barik, Sourav Kumar Dwibedi, Shasanka Sekhar Rout, Satya Ranjan Sahu · 2014
High speed MAC unit is utmostrequirement of today’s VLSI systems and digital signalprocessing applications like FFT, Finite impulse responsefilters, convolution etc.The Digital signal processing (DSP) applications, usually involve many multiplications and accumulations. So, for real time signal processing applications, high speed multiplier-accumulator (MAC) is always a key element to achieve a high-performance digital signal processing application.The speed of MAC depends greatly on the multiplier. In this paper we have proposed an improved time and area efficient MAC unit which employs booth multiplier.The proposed MAC unit is coded in VHDL, synthesized and simulated using Xilinx ISE10.1 software to evaluate the performance results in terms of speed and device utilization. The MAC is implemented on a FPGA device XC3S50-5PQ208 using Xilinx ISE10.1 tool.Our proposed MAC architecture seems to have better performance in terms of speed and area. Â