Area Optimization in Masked Advanced Encryption Standard
R. Vijayabhasker · IOSR Journal of Engineering · 2014
The Advanced Encryption Standard (AES) a symmetric-key block ciphertext published by National Institute of Standards and Technology (NIST) [1].Order to protect a data high throughput masked Advanced Encryption Standard (AES) is used.The masked AES engine uses the unrolling techniques which required extreme level in large field programmable gate array (FPGA).The area optimization in masked AES with an unrolled structure.The mapping of operation from GF(2 8 ) to GF(2 4 ) as much as possible in order to optimize area.The number of mapping is reduced [GF(2 8 ) to GF(2 4 )] and inverse mapping [GF(2 4 ) to GF(2 8 )] operation of the SubBytes by step from zero to nine.In order to compatible, the masked MixColumns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over GF(2 4 ).By moving, mapping and inverse mapping outside the masked AES"s round function, area can be reduced by 20%.