High-Performance VLSI Architecture for Very High-Order FIR Filters Based on Distributed Arithmetic
Takeshi Nozaki, Yoshitaka Tsunekawa, Norio Tayama · Transactions of the Society of Instrument and Control Engineers · 2004
In this paper, we propose a high-performance VLSI architecture for very high-order FIR filters based on distributed arithmetic. By using the distributed arithmetic of which the processing time depends only on word length, small latency can be realized in high-order FIR filters. Also, to decrease drastically power dissipation, the optimum function circuit which we have previously proposed is utilized. Further, the proposed architecture attempts to realize simultaneously smaller latency and lower power dissipation while sampling rate is kept constant. To achieve this objective, we propose newly two methods to utilize linear-phase characteristic using SFA(Serial Full Adder) and a high-speed 4-2 adder. Finally, we evaluate a 240-tap processor based on the proposed architecture. Consequently, we show that the proposed VLSI architecture is very effectively for very high order FIR filters.